1. Technical Field
The present disclosure relates to a method for forming coplanar waveguides in a radio frequency integrated circuit, and more specifically to a method for forming shielded coplanar waveguides.
2. Description of the Related Art
Coplanar waveguides (CPW), or more simply coplanar lines, are currently used in radio frequency integrated circuits (RF), to convey high-frequency signals between two elements of the circuit, for example, between an output amplifier and an antenna. Such lines are particularly current in applications using frequencies ranging from 300 MHz to a few hundreds of GHz.
FIGS. 1 and 2 respectively illustrate in cross-section view and in top view the structure of such a coplanar line. An integrated circuit 1 comprises a semiconductor substrate 2, having active components formed on one of its surfaces. The substrate is topped with an insulating layer 3 in which a coplanar line has been formed. This line comprises a conductive track 4, forming the central conductor and intended to receive the RF signal, surrounded with symmetrical parallel conductive tracks 5 and 6 located in the same plane as track 4, and forming the ground.
Such a coplanar line has a high attenuation coefficient, due to the capacitive coupling between the conductive tracks of the line and the semiconductor substrate and due to the conductivity of this substrate.
FIG. 3 shows the simplified equivalent electric diagram of a coplanar line arranged above a semiconductor substrate of an integrated circuit (the specific inductive and resistive components of the line have deliberately been omitted), as well as three characteristic dimensional parameters, that is, width w of central conductive track 4, spacing g between this track and ground tracks 5 and 6, and thickness h of dielectric 3 separating conductive tracks 4, 5, and 6 from substrate 2. Central conductive track 4 is capacitively coupled by its sides with ground tracks 5 and 6, which coupling is symbolized by capacitors 7 and 8. Further, the three tracks 4, 5, and 6 have a capacitive coupling with semiconductor substrate 2, respectively symbolized by capacitors 9, 10, and 11. Due to the substrate conductivity, there is a resistive coupling between central conductor 4 and lateral conductors 5 and 6, symbolized by resistors 12, through capacitors 9, 10, and 11. Such a coplanar line has a high attenuation coefficient, which limits its transmission performance.
The sizing of such a coplanar line, for a given usage frequency, results from a numbers of constraints. The targeted characteristic impedance, typically 50 ohms, height h of dielectric 3 between the tracks and substrate 2, as well as the relative permittivity of this dielectric, altogether set ratio w/g of the width of central conductor 4 to its spacing from lateral conductors 5 and 6. The resistivity of the conductive material forming the central conductor and the lateral conductors, typically formed of copper, sets the minimum width w of the central conductor, and thus spacing g. The width of lateral conductors 5 and 6, which are conventionally from 2 to 3 times wider than the central conductor, is thus also determined. This results in a total width of the line, which in turn determines the amplitude of the capacitive coupling with the substrate and of the resistive loss due to the substrate conductivity. It is thus not possible to decrease the attenuation coefficient of a coplanar line by only varying the dimensions of the elements forming it.
To reduce the attenuation coefficient of a coplanar line integrated on a semiconductor substrate, it has been provided (Reyes et al, IEEE Microwave Symposium Digest MTT-S International 1994, 1759-1762) to decrease the resistive loss by using a high-resistivity substrate. This solution however has several disadvantages. Such substrates are currently typically ten times more expensive than standard silicon substrates and they typically involve adapting the active component manufacturing steps, which increases integrated circuit manufacturing costs. Besides, there remains in the semiconductor substrate, close to the interface with dielectric 3, a layer having a much higher conductivity than the substrate, due to the presence of charges trapped in the dielectric. It is in practice difficult to avoid the occurrence of such charges and thus to improve the attenuation coefficient of a coplanar line integrated on silicon, even by using a high-resistivity substrate.
The loss due to the substrate can be partly minimized by providing a maximum distance between the line and the substrate, as illustrated in FIG. 4. This drawing shows an integrated circuit 1 comprising a semiconductor substrate 2 coated with a set of metallization levels M1 to M6, which set is currently called BEOL, for Back End Of Line. Such metallization levels conventionally comprise thinner lower metallization levels M1 to M4 and thicker upper metallization levels M5 and M6. Each level comprises conductive tracks 15 and vias 16 connecting conductive tracks 15 to the conductive tracks of the metallization level located immediately underneath. Central conductor 4 and lateral conductors 5 and 6 of a coplanar line have been formed in tracks of upper metallization level M6. The thicknesses, on the one hand, of the insulating layers separating upper metallization levels M5 and M6 and separating levels M4 and M5, on the other hand, from the conductive tracks of upper metallization levels M5 and M6, have been increased with respect to a stack of metallizations of a standard integrated circuit, to maximize total height h of dielectric 3, between substrate 2 and the coplanar line. However, such an approach is limited by current methods for forming metallization levels and does not enable to much exceed thicknesses h of 10 μm. The number of metallization levels may also be increased to increase height h, but this increases the complexity and the cost of the integrated circuit.
It should further be noted that a coplanar line formed on an integrated circuit is a source of electromagnetic radiation capable of creating parasitic signals, in the conductive tracks or the neighboring transistors. It is thus desirable to form a shielding structure around such a line, an embodiment thereof being illustrated in FIG. 4. Stacks of conductive tracks and vias belonging to metallization levels M1 to M5 and forming a Faraday cage around the coplanar line and the insulator as well the adjacent devices have been shown, under the ground tracks and at the periphery thereof. A continuous ground plane, or shielding plane 18, formed in the lower metallization level and forming the bottom of the Faraday cage has also been shown. Such a conductive plane, in front of central conductor 4, however strongly increases the resistive loss and thus increases the attenuation coefficient of the coplanar line.
It should finally be noted that the coplanar lines described hereabove are structure of large bulk, given the submicronic size of current transistors and the tendency to miniaturize circuits. Such lines indeed currently have widths greater than 50 μm and lengths of several millimeters. To decrease the surface of active areas dedicated to these lines, it has been provided to form them on the rear surface of integrated circuits and to connect them to the front surface active components by through conductive connections, currently called TSVs (Through Silicon Vias). Such lines are then formed in a portion of the conductive tracks formed on the rear surface and currently called RDLs (Re-Distribution Layers).
The coplanar lines formed on the rear surface of an integrated circuit however have the same disadvantages as those formed at the front surface, in terms of loss due to the substrate conductivity. Further, since the number of metallization levels is generally smaller at the rear surface (RDL) than at the front surface (BEOL), it is more difficult to provide as large a distance from the line to the substrate as at the front surface.